Communication systems are increasingly developing into packet service communication systems. A packet service communication system refers to a communication system supporting packet services, and is designed to be suitable for high-speed high-capacity data transmission/reception. Particularly, it is known that the next-generation communication system has superior performance gain during high-speed data transmission, and positively considers using Low Density Parity Check (LDPC) codes that can improve the reliability of data transmission by effectively correcting errors caused by noises generated in transmission channels. Meanwhile, in the next-generation data communication system, various schemes have been proposed for high-speed, high-capacity data transmission/reception, such as a Hybrid Automatic Repeat reQuest (HARQ) scheme and an Adaptive Modulation and Coding (AMC) scheme. Various code rates should be supported for the use of the HARQ scheme and the AMC scheme. A puncturing scheme is the typical scheme used for supporting such various code rates. A detailed description of the puncturing scheme will be given below.
A signal transmission apparatus punctures some of the parity bits included in a codeword according to a code rate, and transmits the punctured codeword to a signal reception apparatus. The signal transmission apparatus punctures some of the parity bits included in the codeword using a puncturing pattern, and the puncturing pattern is predefined between the signal transmission apparatus and the signal reception apparatus. For the sake of convenience, a codeword, some of whose parity bits are punctured, will be referred to herein as a ‘punctured codeword’.
The signal transmission apparatus generates parity bit nodes using a parity check matrix, generates a punctured codeword by puncturing some of the generated parity bit nodes according to a puncturing pattern, and transmits the generated punctured codeword to the signal reception apparatus.
The parity check matrix includes the first matrix and the second matrix. The first matrix represents an information part (or systematic part), and the second matrix represents a parity part. For a brief description of the present invention, it is assumed herein that the first matrix includes 32 information bit nodes, and the second matrix includes 64 parity bit nodes (k=32, m=64). Further, the second matrix is a dual-diagonal matrix, and it is assumed that a value of dual-diagonal elements is ‘1’ and a value of the remaining elements is ‘1’.
There are various possible schemes in which a signal reception apparatus receives the punctured codeword and decodes it into an information vector, and a detailed description thereof will be given with reference to FIG. 1.
The signal reception apparatus is assumed to previously recognize the parity check matrix.
Referring to FIG. 1, a scheduling scheme 143 shows a flooding scheduling scheme, in which 0th, 4th, 8th, 12th, 16th, . . . , 60th parity bit nodes 101, 109, 117, 125, 133, . . . , 135 represent parity bit nodes received from the signal transmission apparatus (i.e., parity nodes unpunctured in the signal transmission apparatus), and 1st to 3rd, 5th to 7th, 9th to 11th, 13th to 15th, . . . , 61st to 63rd parity bit nodes 103, 105, 107, 111, 113, 115, 119, 121, 123, 127, 129, 131, . . . , 137, 139, 141 represent parity bit nodes which are not received from the signal transmission apparatus (i.e., parity nodes punctured in the signal transmission apparatus).
The flooding scheduling scheme refers to a scheme of decoding punctured parity bit nodes by parallel-processing the unpunctured parity bit nodes, and the scheme recovers the punctured parity bit nodes by iteratively performing the decoding processing.
Herein, one iteration means an operation of once performing decoding processing on all parity bit nodes, and p iterations mean an operation of p times performing decoding processing on all parity bit nodes. When the punctured parity bit nodes are recovered after decoding processing is iterated p times (i.e., when meaningful values are filled after p iterations are performed), it is referred to as 'p-Step Recovery (p-SR).
The signal reception apparatus for performing decoding using the flooding scheduling scheme, when it performs the first decoding processing, recovers 1st, 3rd, 5th, 7th, 9th, 11th, 13th, 15th, . . . , 61st, 63rd neighboring parity bit nodes 103, 107, 111, 115, 119, 123, 127, 131, . . . , 137, 141 using 0th, 4th, 8th, 12th, 16th, . . . , 60th parity bit nodes 101, 109, 117, 125, 133, . . . , 135. Therefore, the 1st, 3rd, 5th, 7th, 9th, 11th, 13th, 15th, . . . , 61st, 63rd parity bit nodes 103, 107, 111, 115, 119, 123, 127, 131, . . . , 137, 141 become 1-SR parity bit nodes.
The signal reception apparatus, when it performs the second decoding processing, recovers 2nd, 6th, 10th, 14th, . . . , 62nd neighboring parity bit nodes 105, 113, 121, 129, . . . , 139 using the recovered 1st, 3rd, 5th, 7th, 9th, 11th, 13th, 15th, . . . , 61st, 63rd parity bit nodes 103, 107, 111, 115, 119, 123, 127, 131, . . . , 137, 141. Therefore, the 2nd, 6th, 10th, 14th, . . . , 62nd parity bit nodes 105, 113, 121, 129, . . . , 139 become 2-SR parity bit nodes using the flooding scheduling scheme. In this way, when 2-SR is achieved, the signal reception apparatus recovers all parity bit nodes.
Referring to FIG. 1, a scheduling scheme 187 shows a variable node-based serial scheduling scheme, in which 0th, 4th, 8th, 12th, 16th, . . . , 60th parity bit nodes 145, 153, 161, 169, 177, . . . , 179 represent parity bit nodes received from the signal transmission apparatus, and 1st to 3rd, 5th to 7th, 9th to 11th, 13th to 15th, . . . , 61st to 63rd parity bit nodes 147, 149, 151, 155, 157, 159, 163, 165, 167, 171, 173, 175, . . . , 181, 183, 185 represent the parity bit nodes which are not received from the signal transmission apparatus.
The variable node-based serial scheduling scheme refers to a scheme of decoding punctured parity bit nodes by serial-processing the unpunctured parity bit nodes, and the scheme recovers all punctured parity bit nodes by once performing the decoding processing.
In the case where the signal reception apparatus for performing decoding using the variable node-based serial scheduling scheme sequentially decodes the parity bit nodes, since a value of the recovered parity bit node is delivered to the immediately neighboring parity bit node, the signal reception apparatus recovers all parity bit nodes with one decoding processing. That is, the signal reception apparatus recovers the 1st parity bit node 147 using the 0th parity bit node 145, recovers the 2nd parity bit node 149 using the recovered 1st parity bit node 147, and recovers the 3rd parity bit node 151 using the recovered 2nd parity bit node 149. In this manner, the signal reception apparatus recovers the 1st parity bit node 147 through the 63rd parity bit node 185 using the variable node-based serial scheduling scheme, with one decoding processing.
However, regarding the flooding scheduling scheme, since decoding processing is iterated several times when it recovers punctured parity bit nodes, its decoding convergence speed may require a predetermined time.
In addition, as to the variable node-based serial scheduling scheme, when it recovers punctured parity bit nodes, the punctured parity bit nodes may receive meaningless values as a distance between unpunctured parity bit nodes and punctured parity bit nodes is longer, causing a decrease in decoding efficiency.